DesignCon 2012 - Full System Channel Co-optimization for 28Gb/s SerDes FPGA Applications with Stacked Silicon Interconnect Technology

To enable 28 Gb/s transceiver operation, Xilinx has employed many innovative techniques for circuits, packaging and systems. Virtex®-7 HT FPGAs are designed to use Stacked Silicon Interconnect (SSI) technology that relies on an interposer built on low loss package substrate material. Channel loss, reflection loss and crosstalk noise are critical factors in determining system performance at this very high speed. The new concept of SSI in an FPGA device will be introduced. The interposer includes a significant number of TSVs (Through Silicon Vias) for the high speed signals. Technology requirements and manufacturing processes to support 28Gb/s SerDes application will be presented. It is imperative that the signal path including the interposer is accurately modeled over the high frequency operating range by considering all those requirements before design optimization. Detailed design optimization for the interposer has been performed to find optimum design rules by taking into consideration manufacturability and parasitic effects of the TSV’s from DC to high frequency, which can cause major performance degradation. We will also introduce a package design methodology for 28Gb/s SerDes signal support. The package material selection to minimize dielectric loss and trace design to minimize copper/surface roughness loss for the package substrate is very important. In addition, the design topologies to minimize signal loss, reflection loss and crosstalk will be presented. Package and PCB design co-optimization is very important to minimize reflections from solder ball interface. Any single mismatch in the very high speed system can result in the significant closure of the eye diagram. Once full channel analysis has been performed including the optimized silicon interposer model on top of a low loss package substrate and PCB model, the simulation data is then compared to the measured 28Gb/s eye diagram, showing very good correlation. The proposed optimized channel system enables high performance signaling and great visibility of 28Gb/s SerDes enabled FPGA products.